1. Field of the Technology
The present technology relates to a test circuit for evaluating timing accuracy of a clock signal generated by a PLL circuit or the like, and particularly to a built-in type test circuit for examining the effect of jitter in a clock signal at high precision. The present invention also relates to a clock generating circuit such as a PLL circuit and an image sensor equipped with the test circuit, as well as to a delay circuit assembled in the test circuit.
2. Description of the Related Art
In the field of high-speed image processing technologies, the demand has been increased for transferring data at high speed with the use of a highly accurate clock signal which carries less jitter. For example, the mobile telephone technology requires devices for exchanging image data at a rate of 400 Mbps. On the other hand, PLL (phase locked loop) circuits which generate clock signals for high-speed data communication are widely known for multiplying the reference clock to generate high-speed clock signals. As the clock signal generated in such a PLL circuit often carries jitters (fluctuations of the signal waveform), its timing for high-speed communication largely depends on the accuracy of timing actions in the PLL circuit.
It is hence necessary for guaranteeing the timing of the high-speed data communication to test the timing actions in the PLL circuit at an accuracy level of 100 ps or shorter. In common, the accuracy of the timing actions for jitters in the PLL circuit is measured with the use of an external measuring means such as an analog LSI tester or any other high-performance tester. Such an external measuring means is however too low in the measuring accuracy to have a result of the test at a rate of 100 ps or shorter. As disclosed in Japanese Patent Laid-open Publication No. 2003-121505 (referred to as Citation 1 hereinafter), a test circuit and a test method are proposed for examining the effect of jitter in a PLL circuit at higher precision.
The test circuit disclosed in Citation 1 includes, as illustrated in FIG. 8, a delay circuit for producing variable delays (constituted from base delay and adjustable delay), whereby the effect of jitter just after a voltage controlled oscillator (VCO) in the PLL circuit can be measured from a difference of the timing between the output signal of the VCO and a delay signal which has been delayed by one cycle from the output signal in the delay circuit. In addition, the effect of jitter in a duration from the rise to the fall or from the fall to the rise of the output signal of the VCO can be measured from a difference of the timing between the output signal of the VCO and a delay signal which has been delayed by a half the cycle from the output signal. Moreover, the duty ratio of the output signal of the VCO can be calculated from the measurement of jitter with the use of the same circuitry arrangement.
While the test circuit and the test method disclosed in Citation 1 are capable of examining the effect of jitter in a PLL circuit at higher precision, their drawback is that the delay of the delay circuit (the base delay and the adjustable delay) has to be adjusted at higher accuracy for guaranteeing the accuracy of the measurement of jitter in the PLL circuit. Citation 1 however fails to clarify a specific circuitry arrangement for precisely adjusting and determining the delay of the delay circuit.
In general, the PLL circuit is accompanied with a logic circuit and assembled together in one chip. When the delay circuit in the test circuit is implemented by the logic circuit, it can also favorably be assembled in the chip.
FIG. 10 illustrates a circuitry arrangement of the logic circuit which acts as the delay circuit. The circuit shown in FIG. 10 is a variable delay circuit 50 as a part of the delay circuit, in which four delay elements 51, each element composed of two inverter circuits, are connected in series so that their four output signals are received and selectively distributed by a selector 52. The delay circuit hence includes two or more (for example sixteen) of the variable delay circuits 50 connected in series for forming a variable delay circuitry arrangement. Switching a selection of the output signals of the delay elements 51 along the signal path at the selector 52 by a control signal, a desired length of the delay from the input to the output of the variable delay circuit 50 can be determined.
However, this causes the delay from the input to the output of the variable delay circuit 50 to contain a delay component derived from the selector 52 and the extension of the signal path in the variable delay circuit 50 in addition to the delay determined by the delay elements 51 connected in series along the signal path. More particularly, when the selector 52 is switched from one port to another, the extension of the signal path for the output signals of the delay elements 51 and the signal path in the selector 52 are varied. Accordingly, the delay component derived from the selector 52 and the extension of the signal path in the variable delay circuit 50 shall possibly depend on the selecting action of the selector 52. In particular, since the examining of the timing actions in the PLL circuit for high-speed data communications is conducted at a rate of 100 ps or shorter, its delay device needs to be controlled at the resolution of 20 ps or shorter and thus permits no significant variations in the delay along the signal path and in the selector 52.
The performance of the test circuit and the test method disclosed in Citation 1 is based on the following factors; the resolution in the variable delay circuit 50 determines the test resolution, the relationship between the setting of delay to the variable delay circuit 50 and the actual delay is rather monotonous or the delay is simply increased or decreased in proportion to the setting, and the duty ratio of oscillation cycle of a ring oscillator (between high level and low level) at the actual delay measurement is 50% (1:1) or the delay in a rise signal and the delay in a fall signal received by the delay circuit are equal to each other. However, the conventional delay circuit implemented by the logic circuit may have three different disadvantages; (1) lower resolution, (2) non-monotony, and (3) duty error (variations from 50% in the duty rate). The three disadvantages will be explained in more detail.
(1) The lower resolution results from the fact that the resolution of the delay in the variable delay circuit 50 is based on the gate delay determined by the two inverter circuits of the delay element 51. Also, the gate delay-based circuitry arrangement shown in FIG. 10 has a design error derived from variations in the delay along the signal path or across the selector 52 and the delay due to discrepancy in the direction of signal transmission between the delay element 51 and the selector 52. This will disturb the improvement of the circuitry design for minimizing the variations and increasing the resolution. Moreover, since test accuracy or resolution is governed by the gate delay of the two inverter circuits, it is impossible to improve the resolution so as to be shorter than that of the gate delay of the inverter circuits.
(2) When the non-monotony is involved where the actual delay fails to change linearly or monotonously in proportion to the setting of the delay, it may produce a measurement error. The importance of the monotony will now be described referring to FIGS. 11 to 13.
The action of analyzing jitters with the test circuit and test method disclosed in Citation 1 will be explained in brief referring to FIG. 11. It is assumed that the monotony is guaranteed while FIG. 11 illustrates the setting of the delay along the horizontal axis which can be replaced by an actual delay. As the setting of the delay in the delay circuit is varied in steps, the timing of the rise of the output signal from the PLL circuit and the timing of the rise of a delay signal delayed one cycle from the output signal by the delay circuit are compared with each other by a phase comparator. For example, a result of the comparison when the timing of the rise of the output signal from the PLL circuit is later than the timing of the rise of the delay signal is counted by a meas counter to assign the setting of the delay with a count number. This action is schematically illustrated in FIG. 11. The point A represents the maximum of the setting of the delay when the timing of the rise of the output signal from the PLL circuit is earlier than the timing of the rise of a 100% delay signal regardless of the effect of jitter as is equal to the minimum Tmin of the delay of one cycle when a jitter is involved. The point C represents the minimum of the setting of the delay when the timing of the rise of the output signal from the PLL circuit is later than the timing of the rise of a 100% delay signal regardless of the effect of jitter as is equal to the maximum Tmax of the delay of one cycle when a jitter is involved. The point B between the two points A and C represents a state when the timing of the rise of the output signal from the PLL circuit is advanced or delayed from the timing of the rise of the delay signal because of the effect of jitter. Accordingly, the size of a jitter is calculated from a difference Tmax−Tmin of the delay between Tmin at the point A where the count is zero and Tmax at the point C where the count is 100%.
It is now necessary to identify the two points A and C in the two specific factors, the setting of the delay and the count. More specifically, as is explained referring to FIG. 12 where the points where the count is zero are three (A1, A2, and A3), the actual delay increases and shifts monotonously from A1 to A2, A3, B1, . . . in proportion to the elongation of the setting of the delay (shifted towards the lower in the drawing). When the actual delay arrives at the fourth point B1, the count exceeds zero and hence the point A3 prior to the point B1 is designated as the representative point A. Further, as the setting of the delay is elongated gradually, the actual delay increases monotonously and shifts from B1 to B4, B5, C1, C2, C3, and so on. From the point B1 to the point B5, the counter exceeds zero and remains lower than 100%. When the actual delay shifts from B5 to C1, the count reaches 100% and the point C1 is designated as the representative point C. Then, the jitter can be calculated from a difference between the point A3 and the point C1. Alternatively, the setting of the delay may gradually be shortened rather than elongated.
However, when the monotonous relationship between the setting of the delay and the actual delay is lost as shown in FIG. 13, both the points A and C shown in FIG. 11 may hardly be identified by a combination of the setting of the delay and the count. As shown in FIG. 13, the monotonous relationship is held from the point A1 to the point B4 but not from the point C1 to the point C4. As the setting of the delay has gradually been elongated, the count becomes 100% at the point C4. Accordingly, the point C4 may be designated as the representative point C which is duly at the point C1. This will overestimate the effect of jitter. As clarified, the algorithm for the analyzing action is fractured when the monotonous relationship is lost between the setting of the delay and the actual delay and will thus fail to proceed the correct measurement.
(3) The duty error will increase when a difference of the delay between the rise signal and the fall signal in the delay circuit is great. It is needed for measuring the effect of jitter, as shown in FIG. 11, to calculate the actual delays from the settings of the delay at the points A and C. More particularly, the oscillation cycle T in the delay circuit acting as a ring oscillator is first calculated and used for determining a length of the desired delay. Since the ring oscillator is constructed by the variable delay circuit and the single inverter as shown in FIG. 14, the duration Th at the high level of the voltage waveform of the signal at the output port OUT of the variable delay circuit represents the delay T2 in the fall of the input signal at the input port IN because the single inverter inverts the signal level. Also, the duration Tl at the low level of the voltage waveform of the signal at the output port OUT of the variable delay circuit represents the delay T1 in the rise of the input signal at the input port IN. It is hence found that the oscillation cycle T is equal to a sum (T1+T2) of the delay T1 in the rise signal and the delay T2 in the fall signal. More particularly, if the delay circuit has non-symmetrical relationship during the signal transition, the duty ratio in the ring oscillator may hold not 1:1 or turn to T1≠T2. In brief, the delay T1 or T2 will not straightforwardly be determined from the oscillation cycle T. However, the actual delay from the setting of the delay at each of the points A and C has to be either T1 or T2. Assuming that T1=T2 is given for convenience, the delay T1 or T2 is then calculated as ½ the oscillation cycle T in the ring oscillator. As the result, the difference of the delay between the rise signal and the fall signal in the delay circuit will create an error of |T1−T2|/2 between the actual delays at the two points A and C.